Synopsys no CT3

Caros,

Dentre as atividades do Programa CI-Brasil, estamos promovendo um curso de treinamento de uso das ferramentas Synopsys no CT3 em São Paulo, no periodo de 13 a 16 de fevereiro de 2017.

Serão ministrados dois cursos em paralelo:

1- Curso de ferramentas Synopsys para Analog IC Design

 2- Curso de ferramentas Synopsys para Digital IC Design


 

    Analog Schedule  
         
  Monday - 2/13/17 Tuesday - 2/14/17 Wednesday - 2/15/17 Thursday 2/16/17
09:00 Analog Integrated Circuit Design Custom Designer
Schematic, Symbol, SAE
Custom Designer
Layout Editor, DRC
Lab 3: gm/ID
09:30
10:00
10:30 Coffee break Coffee break Coffee break Coffee break
11:00 Custom Designer
Overview, Customization
Custom Designer
Schematic, Symbol, SAE
Lab 2: NMOS Layout Custom Designer
Parasitic Extraction, Corner Analysis
(Esteban Viveros)
11:30
12:00
12:30 Lunch Break Lunch Break Lunch Break Lunch Break
13:00
13:30
14:00 Lab 0: Introduction to Custom Compiler Lab 1: Amplifier (Ideal + Common Source) Lab 2: NMOS Layout Lab 4: Post-layout Simulations
14:30
15:00
15:30 Coffee break Coffee break Coffee break Coffee break
16:00 Lab 0: Introduction to Custom Compiler Lab 1: Amplifier (Ideal + Common Source) Lab 3: gm/ID Lab 4: Post-layout Simulations
16:30
17:00

 

    Digital Schedule  
     
  Monday - 2/13/17 Tuesday - 2/14/17 Wednesday - 2/15/17 Thursday 2/16/17
09:00 Introduction to Synopsys Digital Design Flow Introduction to Design Compiler Introduction to Physical Syntheis with IC Compiler Overview of hierarchical flow, MCMM, Synopsys Physical Guidance
09:30
10:00
10:30 Coffee break Coffee break Coffee break Coffee break
11:00 Introduction to Simulation of Digital Circuits with VCS Introduction to Design Compiler Topographical Physical Syntheis with IC Compiler Overview of Low Power Flow
11:30
12:00
12:30 Lunch Break Lunch Break Lunch Break Lunch Break
13:00
13:30 Lab 1: RTL Simulation Lab 3: Synthesis with
Design Compiler
Lab 5: Place & Route with IC Compiler Overview of Verification Capabilities
14:00
14:30
15:00 Coffee break Coffee break Coffee break Coffee break
15:30 Lab 2: RTL Simulation Lab 4: Synthesis with
Design Compiler
Lab 6: Place & Route with IC Compiler Overview of Signoff
16:00
16:30
17:00

 

 

Os cursos são gratuitos e limitado a 20 alunos por curso.

Os interessados em realizar o curso devem preencher o formulario de inscrição e enviar para a Sara Aparecida de Azevedo ( O endereço de e-mail address está sendo protegido de spambots. Você precisa ativar o JavaScript enabled para vê-lo. )  até 8 de fevereiro de 2017, impreterivelmente.

Os cursos serão ministrados no CT3 no endereço abaixo:

Escola Politécnica da Universidade de São Paulo
Predio da Engenharia Elétrica - Galpão Didático - sala GD-04
Av. Prof. Luciano Gualberto, trav. 3, n0 158
Butantã - São Paulo - SP
Brasil
05508-010
https://goo.gl/maps/LXcJssqmPrp