In 2007, the IC Brazil Program has signed the Software Program License Agreement with Cadence, having access to leading industry EDA tools. Since then, Cadence EDA tools have been intensively used into the Training Centers at Federal University of Rio Grande do Sul in Porto Alegre and at Polytechnic School of University of São Paulo in São Paulo, at Phases I and II (Project Phase), in Digital and Analog design flows.

 

Classes

Basic General:  BG - I. SEMICONDUCTOR BUSINESS, BG - II. IC PROCESSES AND DEVICES, BG - III. PACKAGING, BG - IV. TEST AND DFT

 

Basic Analog: BA - A. ANALOG DESIGN, BA - B1. MIXED-SIGNAL DESIGN, BA - B2. RF DESIGN

 

Basic Digital: BD - A. IC ARCHITECTURE, BD - B. IC DESIGN, BD - C. PHYSICAL DESIGN

 

Tools Digital:

 

  • TD - A1. VERILOG

  • TD - A2. INCISIVE SIMULATOR

  • TD - A3. COMPREHENSIVE COVERAGE

  • TD - B1. UVM COURSE

  • TD - B3. ENTERPRISE MANAGER

  • TD - B4. BASIC STATIC TIMING ANALYSIS

  • TD - B5. CONFORMAL CONSTRAINT DESIGNER

  • TD - B6. RTL COMPILER

  • TD - B7. CONFORMAL LOGIC EQUIVALENCE CHECKING

  • TD - B8. ENCOUNTER TEST

  • TD - C1. FIRST ENCOUNTER

  • TD - C2. NANOROUTE

  • TD - C3. ENCOUNTER TIMING SYSTEM

  • TD - C5. QRC CELL-LEVEL EXTRACTION

  • TD - C6. VIRTUOSO ASSURA - DRC AND LVS

 

Tools Analog:

 

  • TA - A1. ANALOG DESIGN ENVIRONMENT

  • TA - A2. SPECTRE CIRCUIT SIMULATOR

  • TA - A3. ANALOG MODELING - VERILOG A

  • TA - A4. VIRTUOSO LAYOUT EDITOR

  • TA - A5. VIRTUOSO LAYOUT XL EDITOR

  • TA – A6 WICKED - MUNEDA

  • TA - A7. ASSURA VERIFICATION

  • TA - A8. QRC TRANSISTOR-LEVEL EXTRACTION

  • TA - B1. VIRTUOSO AMS DESIGNER

  • TA - B2. SPECTRE RF TOOLS

  • TA - B3. ULTRASIM FULL-CHIP SIMULATOR

 

Support & Maintenance


The EDA environment of IC Brazil Program is supported by NSCAD.

Last update: 22-February-2017.